andre@0: /* This Source Code Form is subject to the terms of the Mozilla Public andre@0: * License, v. 2.0. If a copy of the MPL was not distributed with this andre@0: * file, You can obtain one at http://mozilla.org/MPL/2.0/. */ andre@0: andre@0: /* This implementation is by Ted Krovetz and was submitted to SUPERCOP and andre@0: * marked as public domain. It was been altered to allow for non-aligned inputs andre@0: * and to allow the block counter to be passed in specifically. */ andre@0: andre@0: #include andre@0: andre@0: #include "chacha20.h" andre@0: andre@0: #ifndef CHACHA_RNDS andre@0: #define CHACHA_RNDS 20 /* 8 (high speed), 20 (conservative), 12 (middle) */ andre@0: #endif andre@0: andre@0: /* Architecture-neutral way to specify 16-byte vector of ints */ andre@0: typedef unsigned vec __attribute__ ((vector_size (16))); andre@0: andre@0: /* This implementation is designed for Neon, SSE and AltiVec machines. The andre@0: * following specify how to do certain vector operations efficiently on andre@0: * each architecture, using intrinsics. andre@0: * This implementation supports parallel processing of multiple blocks, andre@0: * including potentially using general-purpose registers. andre@0: */ andre@0: #if __ARM_NEON__ andre@0: #include andre@0: #define GPR_TOO 1 andre@0: #define VBPI 2 andre@0: #define ONE (vec)vsetq_lane_u32(1,vdupq_n_u32(0),0) andre@0: #define LOAD(m) (vec)(*((vec*)(m))) andre@0: #define STORE(m,r) (*((vec*)(m))) = (r) andre@0: #define ROTV1(x) (vec)vextq_u32((uint32x4_t)x,(uint32x4_t)x,1) andre@0: #define ROTV2(x) (vec)vextq_u32((uint32x4_t)x,(uint32x4_t)x,2) andre@0: #define ROTV3(x) (vec)vextq_u32((uint32x4_t)x,(uint32x4_t)x,3) andre@0: #define ROTW16(x) (vec)vrev32q_u16((uint16x8_t)x) andre@0: #if __clang__ andre@0: #define ROTW7(x) (x << ((vec){ 7, 7, 7, 7})) ^ (x >> ((vec){25,25,25,25})) andre@0: #define ROTW8(x) (x << ((vec){ 8, 8, 8, 8})) ^ (x >> ((vec){24,24,24,24})) andre@0: #define ROTW12(x) (x << ((vec){12,12,12,12})) ^ (x >> ((vec){20,20,20,20})) andre@0: #else andre@0: #define ROTW7(x) (vec)vsriq_n_u32(vshlq_n_u32((uint32x4_t)x,7),(uint32x4_t)x,25) andre@0: #define ROTW8(x) (vec)vsriq_n_u32(vshlq_n_u32((uint32x4_t)x,8),(uint32x4_t)x,24) andre@0: #define ROTW12(x) (vec)vsriq_n_u32(vshlq_n_u32((uint32x4_t)x,12),(uint32x4_t)x,20) andre@0: #endif andre@0: #elif __SSE2__ andre@0: #include andre@0: #define GPR_TOO 0 andre@0: #if __clang__ andre@0: #define VBPI 4 andre@0: #else andre@0: #define VBPI 3 andre@0: #endif andre@0: #define ONE (vec)_mm_set_epi32(0,0,0,1) andre@0: #define LOAD(m) (vec)_mm_loadu_si128((__m128i*)(m)) andre@0: #define STORE(m,r) _mm_storeu_si128((__m128i*)(m), (__m128i) (r)) andre@0: #define ROTV1(x) (vec)_mm_shuffle_epi32((__m128i)x,_MM_SHUFFLE(0,3,2,1)) andre@0: #define ROTV2(x) (vec)_mm_shuffle_epi32((__m128i)x,_MM_SHUFFLE(1,0,3,2)) andre@0: #define ROTV3(x) (vec)_mm_shuffle_epi32((__m128i)x,_MM_SHUFFLE(2,1,0,3)) andre@0: #define ROTW7(x) (vec)(_mm_slli_epi32((__m128i)x, 7) ^ _mm_srli_epi32((__m128i)x,25)) andre@0: #define ROTW12(x) (vec)(_mm_slli_epi32((__m128i)x,12) ^ _mm_srli_epi32((__m128i)x,20)) andre@0: #if __SSSE3__ andre@0: #include andre@0: #define ROTW8(x) (vec)_mm_shuffle_epi8((__m128i)x,_mm_set_epi8(14,13,12,15,10,9,8,11,6,5,4,7,2,1,0,3)) andre@0: #define ROTW16(x) (vec)_mm_shuffle_epi8((__m128i)x,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)) andre@0: #else andre@0: #define ROTW8(x) (vec)(_mm_slli_epi32((__m128i)x, 8) ^ _mm_srli_epi32((__m128i)x,24)) andre@0: #define ROTW16(x) (vec)(_mm_slli_epi32((__m128i)x,16) ^ _mm_srli_epi32((__m128i)x,16)) andre@0: #endif andre@0: #else andre@0: #error -- Implementation supports only machines with neon or SSE2 andre@0: #endif andre@0: andre@0: #ifndef REVV_BE andre@0: #define REVV_BE(x) (x) andre@0: #endif andre@0: andre@0: #ifndef REVW_BE andre@0: #define REVW_BE(x) (x) andre@0: #endif andre@0: andre@0: #define BPI (VBPI + GPR_TOO) /* Blocks computed per loop iteration */ andre@0: andre@0: #define DQROUND_VECTORS(a,b,c,d) \ andre@0: a += b; d ^= a; d = ROTW16(d); \ andre@0: c += d; b ^= c; b = ROTW12(b); \ andre@0: a += b; d ^= a; d = ROTW8(d); \ andre@0: c += d; b ^= c; b = ROTW7(b); \ andre@0: b = ROTV1(b); c = ROTV2(c); d = ROTV3(d); \ andre@0: a += b; d ^= a; d = ROTW16(d); \ andre@0: c += d; b ^= c; b = ROTW12(b); \ andre@0: a += b; d ^= a; d = ROTW8(d); \ andre@0: c += d; b ^= c; b = ROTW7(b); \ andre@0: b = ROTV3(b); c = ROTV2(c); d = ROTV1(d); andre@0: andre@0: #define QROUND_WORDS(a,b,c,d) \ andre@0: a = a+b; d ^= a; d = d<<16 | d>>16; \ andre@0: c = c+d; b ^= c; b = b<<12 | b>>20; \ andre@0: a = a+b; d ^= a; d = d<< 8 | d>>24; \ andre@0: c = c+d; b ^= c; b = b<< 7 | b>>25; andre@0: andre@0: #define WRITE_XOR(in, op, d, v0, v1, v2, v3) \ andre@0: STORE(op + d + 0, LOAD(in + d + 0) ^ REVV_BE(v0)); \ andre@0: STORE(op + d + 4, LOAD(in + d + 4) ^ REVV_BE(v1)); \ andre@0: STORE(op + d + 8, LOAD(in + d + 8) ^ REVV_BE(v2)); \ andre@0: STORE(op + d +12, LOAD(in + d +12) ^ REVV_BE(v3)); andre@0: andre@0: void ChaCha20XOR( andre@0: unsigned char *out, andre@0: const unsigned char *in, andre@0: unsigned int inlen, andre@0: const unsigned char key[32], andre@0: const unsigned char nonce[8], andre@0: uint64_t counter) andre@0: { andre@0: unsigned iters, i, *op=(unsigned *)out, *ip=(unsigned *)in, *kp; andre@0: #if defined(__ARM_NEON__) andre@0: unsigned *np; andre@0: #endif andre@0: vec s0, s1, s2, s3; andre@0: #if !defined(__ARM_NEON__) && !defined(__SSE2__) andre@0: __attribute__ ((aligned (16))) unsigned key[8], nonce[4]; andre@0: #endif andre@0: __attribute__ ((aligned (16))) unsigned chacha_const[] = andre@0: {0x61707865,0x3320646E,0x79622D32,0x6B206574}; andre@0: #if defined(__ARM_NEON__) || defined(__SSE2__) andre@0: kp = (unsigned *)key; andre@0: #else andre@0: ((vec *)key)[0] = REVV_BE(((vec *)key)[0]); andre@0: ((vec *)key)[1] = REVV_BE(((vec *)key)[1]); andre@0: nonce[0] = REVW_BE(((unsigned *)nonce)[0]); andre@0: nonce[1] = REVW_BE(((unsigned *)nonce)[1]); andre@0: nonce[2] = REVW_BE(((unsigned *)nonce)[2]); andre@0: nonce[3] = REVW_BE(((unsigned *)nonce)[3]); andre@0: kp = (unsigned *)key; andre@0: np = (unsigned *)nonce; andre@0: #endif andre@0: #if defined(__ARM_NEON__) andre@0: np = (unsigned*) nonce; andre@0: #endif andre@0: s0 = LOAD(chacha_const); andre@0: s1 = LOAD(&((vec*)kp)[0]); andre@0: s2 = LOAD(&((vec*)kp)[1]); andre@0: s3 = (vec) { andre@0: counter & 0xffffffff, andre@0: counter >> 32, andre@0: ((uint32_t*)nonce)[0], andre@0: ((uint32_t*)nonce)[1] andre@0: }; andre@0: andre@0: for (iters = 0; iters < inlen/(BPI*64); iters++) { andre@0: #if GPR_TOO andre@0: register unsigned x0, x1, x2, x3, x4, x5, x6, x7, x8, andre@0: x9, x10, x11, x12, x13, x14, x15; andre@0: #endif andre@0: #if VBPI > 2 andre@0: vec v8,v9,v10,v11; andre@0: #endif andre@0: #if VBPI > 3 andre@0: vec v12,v13,v14,v15; andre@0: #endif andre@0: andre@0: vec v0,v1,v2,v3,v4,v5,v6,v7; andre@0: v4 = v0 = s0; v5 = v1 = s1; v6 = v2 = s2; v3 = s3; andre@0: v7 = v3 + ONE; andre@0: #if VBPI > 2 andre@0: v8 = v4; v9 = v5; v10 = v6; andre@0: v11 = v7 + ONE; andre@0: #endif andre@0: #if VBPI > 3 andre@0: v12 = v8; v13 = v9; v14 = v10; andre@0: v15 = v11 + ONE; andre@0: #endif andre@0: #if GPR_TOO andre@0: x0 = chacha_const[0]; x1 = chacha_const[1]; andre@0: x2 = chacha_const[2]; x3 = chacha_const[3]; andre@0: x4 = kp[0]; x5 = kp[1]; x6 = kp[2]; x7 = kp[3]; andre@0: x8 = kp[4]; x9 = kp[5]; x10 = kp[6]; x11 = kp[7]; andre@0: x12 = (counter & 0xffffffff)+BPI*iters+(BPI-1); x13 = counter >> 32; andre@0: x14 = np[0]; x15 = np[1]; andre@0: #endif andre@0: for (i = CHACHA_RNDS/2; i; i--) { andre@0: DQROUND_VECTORS(v0,v1,v2,v3) andre@0: DQROUND_VECTORS(v4,v5,v6,v7) andre@0: #if VBPI > 2 andre@0: DQROUND_VECTORS(v8,v9,v10,v11) andre@0: #endif andre@0: #if VBPI > 3 andre@0: DQROUND_VECTORS(v12,v13,v14,v15) andre@0: #endif andre@0: #if GPR_TOO andre@0: QROUND_WORDS( x0, x4, x8,x12) andre@0: QROUND_WORDS( x1, x5, x9,x13) andre@0: QROUND_WORDS( x2, x6,x10,x14) andre@0: QROUND_WORDS( x3, x7,x11,x15) andre@0: QROUND_WORDS( x0, x5,x10,x15) andre@0: QROUND_WORDS( x1, x6,x11,x12) andre@0: QROUND_WORDS( x2, x7, x8,x13) andre@0: QROUND_WORDS( x3, x4, x9,x14) andre@0: #endif andre@0: } andre@0: andre@0: WRITE_XOR(ip, op, 0, v0+s0, v1+s1, v2+s2, v3+s3) andre@0: s3 += ONE; andre@0: WRITE_XOR(ip, op, 16, v4+s0, v5+s1, v6+s2, v7+s3) andre@0: s3 += ONE; andre@0: #if VBPI > 2 andre@0: WRITE_XOR(ip, op, 32, v8+s0, v9+s1, v10+s2, v11+s3) andre@0: s3 += ONE; andre@0: #endif andre@0: #if VBPI > 3 andre@0: WRITE_XOR(ip, op, 48, v12+s0, v13+s1, v14+s2, v15+s3) andre@0: s3 += ONE; andre@0: #endif andre@0: ip += VBPI*16; andre@0: op += VBPI*16; andre@0: #if GPR_TOO andre@0: op[0] = REVW_BE(REVW_BE(ip[0]) ^ (x0 + chacha_const[0])); andre@0: op[1] = REVW_BE(REVW_BE(ip[1]) ^ (x1 + chacha_const[1])); andre@0: op[2] = REVW_BE(REVW_BE(ip[2]) ^ (x2 + chacha_const[2])); andre@0: op[3] = REVW_BE(REVW_BE(ip[3]) ^ (x3 + chacha_const[3])); andre@0: op[4] = REVW_BE(REVW_BE(ip[4]) ^ (x4 + kp[0])); andre@0: op[5] = REVW_BE(REVW_BE(ip[5]) ^ (x5 + kp[1])); andre@0: op[6] = REVW_BE(REVW_BE(ip[6]) ^ (x6 + kp[2])); andre@0: op[7] = REVW_BE(REVW_BE(ip[7]) ^ (x7 + kp[3])); andre@0: op[8] = REVW_BE(REVW_BE(ip[8]) ^ (x8 + kp[4])); andre@0: op[9] = REVW_BE(REVW_BE(ip[9]) ^ (x9 + kp[5])); andre@0: op[10] = REVW_BE(REVW_BE(ip[10]) ^ (x10 + kp[6])); andre@0: op[11] = REVW_BE(REVW_BE(ip[11]) ^ (x11 + kp[7])); andre@0: op[12] = REVW_BE(REVW_BE(ip[12]) ^ (x12 + (counter & 0xffffffff)+BPI*iters+(BPI-1))); andre@0: op[13] = REVW_BE(REVW_BE(ip[13]) ^ (x13 + (counter >> 32))); andre@0: op[14] = REVW_BE(REVW_BE(ip[14]) ^ (x14 + np[0])); andre@0: op[15] = REVW_BE(REVW_BE(ip[15]) ^ (x15 + np[1])); andre@0: s3 += ONE; andre@0: ip += 16; andre@0: op += 16; andre@0: #endif andre@0: } andre@0: andre@0: for (iters = inlen%(BPI*64)/64; iters != 0; iters--) { andre@0: vec v0 = s0, v1 = s1, v2 = s2, v3 = s3; andre@0: for (i = CHACHA_RNDS/2; i; i--) { andre@0: DQROUND_VECTORS(v0,v1,v2,v3); andre@0: } andre@0: WRITE_XOR(ip, op, 0, v0+s0, v1+s1, v2+s2, v3+s3) andre@0: s3 += ONE; andre@0: ip += 16; andre@0: op += 16; andre@0: } andre@0: andre@0: inlen = inlen % 64; andre@0: if (inlen) { andre@0: __attribute__ ((aligned (16))) vec buf[4]; andre@0: vec v0,v1,v2,v3; andre@0: v0 = s0; v1 = s1; v2 = s2; v3 = s3; andre@0: for (i = CHACHA_RNDS/2; i; i--) { andre@0: DQROUND_VECTORS(v0,v1,v2,v3); andre@0: } andre@0: andre@0: if (inlen >= 16) { andre@0: STORE(op + 0, LOAD(ip + 0) ^ REVV_BE(v0 + s0)); andre@0: if (inlen >= 32) { andre@0: STORE(op + 4, LOAD(ip + 4) ^ REVV_BE(v1 + s1)); andre@0: if (inlen >= 48) { andre@0: STORE(op + 8, LOAD(ip + 8) ^ REVV_BE(v2 + s2)); andre@0: buf[3] = REVV_BE(v3 + s3); andre@0: } else { andre@0: buf[2] = REVV_BE(v2 + s2); andre@0: } andre@0: } else { andre@0: buf[1] = REVV_BE(v1 + s1); andre@0: } andre@0: } else { andre@0: buf[0] = REVV_BE(v0 + s0); andre@0: } andre@0: andre@0: for (i=inlen & ~15; i