Mercurial > trustbridge > nss-cmake-static
annotate nss/lib/freebl/chacha20/chacha20_vec.c @ 0:1e5118fa0cb1
This is NSS with a Cmake Buildsyste
To compile a static NSS library for Windows we've used the
Chromium-NSS fork and added a Cmake buildsystem to compile
it statically for Windows. See README.chromium for chromium
changes and README.trustbridge for our modifications.
author | Andre Heinecke <andre.heinecke@intevation.de> |
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date | Mon, 28 Jul 2014 10:47:06 +0200 |
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rev | line source |
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0
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1 /* This Source Code Form is subject to the terms of the Mozilla Public |
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2 * License, v. 2.0. If a copy of the MPL was not distributed with this |
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3 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */ |
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4 |
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5 /* This implementation is by Ted Krovetz and was submitted to SUPERCOP and |
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6 * marked as public domain. It was been altered to allow for non-aligned inputs |
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7 * and to allow the block counter to be passed in specifically. */ |
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8 |
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9 #include <string.h> |
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10 |
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11 #include "chacha20.h" |
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12 |
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13 #ifndef CHACHA_RNDS |
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14 #define CHACHA_RNDS 20 /* 8 (high speed), 20 (conservative), 12 (middle) */ |
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15 #endif |
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16 |
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17 /* Architecture-neutral way to specify 16-byte vector of ints */ |
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18 typedef unsigned vec __attribute__ ((vector_size (16))); |
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19 |
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20 /* This implementation is designed for Neon, SSE and AltiVec machines. The |
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21 * following specify how to do certain vector operations efficiently on |
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22 * each architecture, using intrinsics. |
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23 * This implementation supports parallel processing of multiple blocks, |
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24 * including potentially using general-purpose registers. |
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25 */ |
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26 #if __ARM_NEON__ |
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27 #include <arm_neon.h> |
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28 #define GPR_TOO 1 |
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29 #define VBPI 2 |
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30 #define ONE (vec)vsetq_lane_u32(1,vdupq_n_u32(0),0) |
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31 #define LOAD(m) (vec)(*((vec*)(m))) |
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32 #define STORE(m,r) (*((vec*)(m))) = (r) |
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33 #define ROTV1(x) (vec)vextq_u32((uint32x4_t)x,(uint32x4_t)x,1) |
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34 #define ROTV2(x) (vec)vextq_u32((uint32x4_t)x,(uint32x4_t)x,2) |
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35 #define ROTV3(x) (vec)vextq_u32((uint32x4_t)x,(uint32x4_t)x,3) |
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36 #define ROTW16(x) (vec)vrev32q_u16((uint16x8_t)x) |
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37 #if __clang__ |
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38 #define ROTW7(x) (x << ((vec){ 7, 7, 7, 7})) ^ (x >> ((vec){25,25,25,25})) |
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39 #define ROTW8(x) (x << ((vec){ 8, 8, 8, 8})) ^ (x >> ((vec){24,24,24,24})) |
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40 #define ROTW12(x) (x << ((vec){12,12,12,12})) ^ (x >> ((vec){20,20,20,20})) |
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41 #else |
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42 #define ROTW7(x) (vec)vsriq_n_u32(vshlq_n_u32((uint32x4_t)x,7),(uint32x4_t)x,25) |
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43 #define ROTW8(x) (vec)vsriq_n_u32(vshlq_n_u32((uint32x4_t)x,8),(uint32x4_t)x,24) |
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44 #define ROTW12(x) (vec)vsriq_n_u32(vshlq_n_u32((uint32x4_t)x,12),(uint32x4_t)x,20) |
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45 #endif |
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46 #elif __SSE2__ |
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47 #include <emmintrin.h> |
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48 #define GPR_TOO 0 |
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49 #if __clang__ |
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50 #define VBPI 4 |
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51 #else |
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52 #define VBPI 3 |
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53 #endif |
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54 #define ONE (vec)_mm_set_epi32(0,0,0,1) |
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55 #define LOAD(m) (vec)_mm_loadu_si128((__m128i*)(m)) |
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56 #define STORE(m,r) _mm_storeu_si128((__m128i*)(m), (__m128i) (r)) |
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57 #define ROTV1(x) (vec)_mm_shuffle_epi32((__m128i)x,_MM_SHUFFLE(0,3,2,1)) |
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58 #define ROTV2(x) (vec)_mm_shuffle_epi32((__m128i)x,_MM_SHUFFLE(1,0,3,2)) |
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59 #define ROTV3(x) (vec)_mm_shuffle_epi32((__m128i)x,_MM_SHUFFLE(2,1,0,3)) |
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60 #define ROTW7(x) (vec)(_mm_slli_epi32((__m128i)x, 7) ^ _mm_srli_epi32((__m128i)x,25)) |
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61 #define ROTW12(x) (vec)(_mm_slli_epi32((__m128i)x,12) ^ _mm_srli_epi32((__m128i)x,20)) |
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62 #if __SSSE3__ |
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63 #include <tmmintrin.h> |
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64 #define ROTW8(x) (vec)_mm_shuffle_epi8((__m128i)x,_mm_set_epi8(14,13,12,15,10,9,8,11,6,5,4,7,2,1,0,3)) |
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65 #define ROTW16(x) (vec)_mm_shuffle_epi8((__m128i)x,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)) |
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66 #else |
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67 #define ROTW8(x) (vec)(_mm_slli_epi32((__m128i)x, 8) ^ _mm_srli_epi32((__m128i)x,24)) |
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68 #define ROTW16(x) (vec)(_mm_slli_epi32((__m128i)x,16) ^ _mm_srli_epi32((__m128i)x,16)) |
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69 #endif |
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70 #else |
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71 #error -- Implementation supports only machines with neon or SSE2 |
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72 #endif |
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73 |
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74 #ifndef REVV_BE |
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75 #define REVV_BE(x) (x) |
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76 #endif |
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77 |
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78 #ifndef REVW_BE |
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79 #define REVW_BE(x) (x) |
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80 #endif |
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81 |
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82 #define BPI (VBPI + GPR_TOO) /* Blocks computed per loop iteration */ |
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83 |
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84 #define DQROUND_VECTORS(a,b,c,d) \ |
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85 a += b; d ^= a; d = ROTW16(d); \ |
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86 c += d; b ^= c; b = ROTW12(b); \ |
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87 a += b; d ^= a; d = ROTW8(d); \ |
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88 c += d; b ^= c; b = ROTW7(b); \ |
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89 b = ROTV1(b); c = ROTV2(c); d = ROTV3(d); \ |
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90 a += b; d ^= a; d = ROTW16(d); \ |
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91 c += d; b ^= c; b = ROTW12(b); \ |
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92 a += b; d ^= a; d = ROTW8(d); \ |
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93 c += d; b ^= c; b = ROTW7(b); \ |
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94 b = ROTV3(b); c = ROTV2(c); d = ROTV1(d); |
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95 |
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96 #define QROUND_WORDS(a,b,c,d) \ |
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97 a = a+b; d ^= a; d = d<<16 | d>>16; \ |
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98 c = c+d; b ^= c; b = b<<12 | b>>20; \ |
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99 a = a+b; d ^= a; d = d<< 8 | d>>24; \ |
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100 c = c+d; b ^= c; b = b<< 7 | b>>25; |
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101 |
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102 #define WRITE_XOR(in, op, d, v0, v1, v2, v3) \ |
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103 STORE(op + d + 0, LOAD(in + d + 0) ^ REVV_BE(v0)); \ |
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104 STORE(op + d + 4, LOAD(in + d + 4) ^ REVV_BE(v1)); \ |
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105 STORE(op + d + 8, LOAD(in + d + 8) ^ REVV_BE(v2)); \ |
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106 STORE(op + d +12, LOAD(in + d +12) ^ REVV_BE(v3)); |
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107 |
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108 void ChaCha20XOR( |
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109 unsigned char *out, |
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110 const unsigned char *in, |
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111 unsigned int inlen, |
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112 const unsigned char key[32], |
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113 const unsigned char nonce[8], |
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114 uint64_t counter) |
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115 { |
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116 unsigned iters, i, *op=(unsigned *)out, *ip=(unsigned *)in, *kp; |
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117 #if defined(__ARM_NEON__) |
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118 unsigned *np; |
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119 #endif |
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120 vec s0, s1, s2, s3; |
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121 #if !defined(__ARM_NEON__) && !defined(__SSE2__) |
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122 __attribute__ ((aligned (16))) unsigned key[8], nonce[4]; |
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123 #endif |
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124 __attribute__ ((aligned (16))) unsigned chacha_const[] = |
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125 {0x61707865,0x3320646E,0x79622D32,0x6B206574}; |
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126 #if defined(__ARM_NEON__) || defined(__SSE2__) |
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127 kp = (unsigned *)key; |
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128 #else |
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129 ((vec *)key)[0] = REVV_BE(((vec *)key)[0]); |
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130 ((vec *)key)[1] = REVV_BE(((vec *)key)[1]); |
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131 nonce[0] = REVW_BE(((unsigned *)nonce)[0]); |
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132 nonce[1] = REVW_BE(((unsigned *)nonce)[1]); |
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133 nonce[2] = REVW_BE(((unsigned *)nonce)[2]); |
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134 nonce[3] = REVW_BE(((unsigned *)nonce)[3]); |
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135 kp = (unsigned *)key; |
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136 np = (unsigned *)nonce; |
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137 #endif |
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138 #if defined(__ARM_NEON__) |
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139 np = (unsigned*) nonce; |
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140 #endif |
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141 s0 = LOAD(chacha_const); |
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142 s1 = LOAD(&((vec*)kp)[0]); |
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143 s2 = LOAD(&((vec*)kp)[1]); |
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144 s3 = (vec) { |
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145 counter & 0xffffffff, |
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146 counter >> 32, |
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147 ((uint32_t*)nonce)[0], |
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148 ((uint32_t*)nonce)[1] |
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149 }; |
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150 |
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151 for (iters = 0; iters < inlen/(BPI*64); iters++) { |
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152 #if GPR_TOO |
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153 register unsigned x0, x1, x2, x3, x4, x5, x6, x7, x8, |
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154 x9, x10, x11, x12, x13, x14, x15; |
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155 #endif |
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156 #if VBPI > 2 |
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157 vec v8,v9,v10,v11; |
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158 #endif |
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159 #if VBPI > 3 |
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160 vec v12,v13,v14,v15; |
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161 #endif |
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162 |
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163 vec v0,v1,v2,v3,v4,v5,v6,v7; |
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164 v4 = v0 = s0; v5 = v1 = s1; v6 = v2 = s2; v3 = s3; |
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165 v7 = v3 + ONE; |
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166 #if VBPI > 2 |
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167 v8 = v4; v9 = v5; v10 = v6; |
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168 v11 = v7 + ONE; |
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169 #endif |
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170 #if VBPI > 3 |
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171 v12 = v8; v13 = v9; v14 = v10; |
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172 v15 = v11 + ONE; |
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173 #endif |
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174 #if GPR_TOO |
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175 x0 = chacha_const[0]; x1 = chacha_const[1]; |
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176 x2 = chacha_const[2]; x3 = chacha_const[3]; |
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177 x4 = kp[0]; x5 = kp[1]; x6 = kp[2]; x7 = kp[3]; |
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178 x8 = kp[4]; x9 = kp[5]; x10 = kp[6]; x11 = kp[7]; |
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179 x12 = (counter & 0xffffffff)+BPI*iters+(BPI-1); x13 = counter >> 32; |
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180 x14 = np[0]; x15 = np[1]; |
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181 #endif |
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182 for (i = CHACHA_RNDS/2; i; i--) { |
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183 DQROUND_VECTORS(v0,v1,v2,v3) |
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184 DQROUND_VECTORS(v4,v5,v6,v7) |
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185 #if VBPI > 2 |
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186 DQROUND_VECTORS(v8,v9,v10,v11) |
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187 #endif |
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188 #if VBPI > 3 |
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189 DQROUND_VECTORS(v12,v13,v14,v15) |
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190 #endif |
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191 #if GPR_TOO |
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192 QROUND_WORDS( x0, x4, x8,x12) |
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193 QROUND_WORDS( x1, x5, x9,x13) |
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194 QROUND_WORDS( x2, x6,x10,x14) |
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195 QROUND_WORDS( x3, x7,x11,x15) |
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196 QROUND_WORDS( x0, x5,x10,x15) |
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197 QROUND_WORDS( x1, x6,x11,x12) |
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198 QROUND_WORDS( x2, x7, x8,x13) |
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199 QROUND_WORDS( x3, x4, x9,x14) |
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200 #endif |
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201 } |
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202 |
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203 WRITE_XOR(ip, op, 0, v0+s0, v1+s1, v2+s2, v3+s3) |
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204 s3 += ONE; |
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205 WRITE_XOR(ip, op, 16, v4+s0, v5+s1, v6+s2, v7+s3) |
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206 s3 += ONE; |
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207 #if VBPI > 2 |
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208 WRITE_XOR(ip, op, 32, v8+s0, v9+s1, v10+s2, v11+s3) |
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209 s3 += ONE; |
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210 #endif |
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211 #if VBPI > 3 |
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212 WRITE_XOR(ip, op, 48, v12+s0, v13+s1, v14+s2, v15+s3) |
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213 s3 += ONE; |
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214 #endif |
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215 ip += VBPI*16; |
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216 op += VBPI*16; |
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217 #if GPR_TOO |
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218 op[0] = REVW_BE(REVW_BE(ip[0]) ^ (x0 + chacha_const[0])); |
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219 op[1] = REVW_BE(REVW_BE(ip[1]) ^ (x1 + chacha_const[1])); |
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220 op[2] = REVW_BE(REVW_BE(ip[2]) ^ (x2 + chacha_const[2])); |
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221 op[3] = REVW_BE(REVW_BE(ip[3]) ^ (x3 + chacha_const[3])); |
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222 op[4] = REVW_BE(REVW_BE(ip[4]) ^ (x4 + kp[0])); |
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223 op[5] = REVW_BE(REVW_BE(ip[5]) ^ (x5 + kp[1])); |
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224 op[6] = REVW_BE(REVW_BE(ip[6]) ^ (x6 + kp[2])); |
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225 op[7] = REVW_BE(REVW_BE(ip[7]) ^ (x7 + kp[3])); |
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226 op[8] = REVW_BE(REVW_BE(ip[8]) ^ (x8 + kp[4])); |
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227 op[9] = REVW_BE(REVW_BE(ip[9]) ^ (x9 + kp[5])); |
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228 op[10] = REVW_BE(REVW_BE(ip[10]) ^ (x10 + kp[6])); |
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229 op[11] = REVW_BE(REVW_BE(ip[11]) ^ (x11 + kp[7])); |
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230 op[12] = REVW_BE(REVW_BE(ip[12]) ^ (x12 + (counter & 0xffffffff)+BPI*iters+(BPI-1))); |
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231 op[13] = REVW_BE(REVW_BE(ip[13]) ^ (x13 + (counter >> 32))); |
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232 op[14] = REVW_BE(REVW_BE(ip[14]) ^ (x14 + np[0])); |
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233 op[15] = REVW_BE(REVW_BE(ip[15]) ^ (x15 + np[1])); |
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234 s3 += ONE; |
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235 ip += 16; |
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236 op += 16; |
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237 #endif |
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238 } |
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239 |
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240 for (iters = inlen%(BPI*64)/64; iters != 0; iters--) { |
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241 vec v0 = s0, v1 = s1, v2 = s2, v3 = s3; |
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242 for (i = CHACHA_RNDS/2; i; i--) { |
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243 DQROUND_VECTORS(v0,v1,v2,v3); |
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244 } |
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245 WRITE_XOR(ip, op, 0, v0+s0, v1+s1, v2+s2, v3+s3) |
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246 s3 += ONE; |
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247 ip += 16; |
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248 op += 16; |
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249 } |
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250 |
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251 inlen = inlen % 64; |
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252 if (inlen) { |
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253 __attribute__ ((aligned (16))) vec buf[4]; |
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254 vec v0,v1,v2,v3; |
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255 v0 = s0; v1 = s1; v2 = s2; v3 = s3; |
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256 for (i = CHACHA_RNDS/2; i; i--) { |
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257 DQROUND_VECTORS(v0,v1,v2,v3); |
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258 } |
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259 |
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260 if (inlen >= 16) { |
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261 STORE(op + 0, LOAD(ip + 0) ^ REVV_BE(v0 + s0)); |
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262 if (inlen >= 32) { |
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263 STORE(op + 4, LOAD(ip + 4) ^ REVV_BE(v1 + s1)); |
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264 if (inlen >= 48) { |
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265 STORE(op + 8, LOAD(ip + 8) ^ REVV_BE(v2 + s2)); |
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266 buf[3] = REVV_BE(v3 + s3); |
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267 } else { |
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268 buf[2] = REVV_BE(v2 + s2); |
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269 } |
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270 } else { |
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271 buf[1] = REVV_BE(v1 + s1); |
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272 } |
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273 } else { |
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274 buf[0] = REVV_BE(v0 + s0); |
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275 } |
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276 |
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277 for (i=inlen & ~15; i<inlen; i++) { |
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278 ((char *)op)[i] = ((char *)ip)[i] ^ ((char *)buf)[i]; |
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279 } |
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280 } |
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281 } |